IC4X has successfully completed the development and tapeout of a Dual 1GS/s DAC chip, fabricated using TSMC’s 28HPC+ process. This cutting-edge DAC solution, named DAC10_1GS_28HPC+_DUAL, delivers high-performance digital-to-analog conversion with exceptional precision and flexibility. Designed to meet demanding application requirements, the IP offers advanced features such as dual 10-bit, 1GS/s current-steering DACs with configurable clock phases and fine-tuned gain control for optimal performance. Below is a detailed overview of its key specifications and features.

  • Dual 10-bit 1GS/s current-steering DAC IP
  • Clkgen block generates clocks for DAC0 and 
DAC1 with phase relation 0°/0°, 0°/90°, 
0°/180°, or 180°/0°.
  • Blocks delay0 and delay1 allow to shift the 
delay with 60fs resolution (± 2ps total range)
  • Coarse gain control (sets full scale to 
500mVPPD, 750mVPPD, or 1VPPD)
  • Fine gain control (0.05% resolution) to 
minimize gain error between DAC1 and DAC2 
(10% range)
  • DAC outputs connect to external 50Ohm 
resistor to GND (or neg. supply)
  • IP includes bandgap (700mV)
  • IP employs reference current (IREF) generator 
requiring 8.3kW external resistor to GND
  • Digital CMOS input data levels of 1.8V/0V, 
single-ended
  • IP provides phase-corrected output clock 
(Delay 2) for robust FPGA/input data 
resampling
  • Delay 2 enables to shift digital output clock 
with 100ps resolution up to 1.5ns. An 
additional bit allows to invert the clock output
  • The retiming block employs 2 flags 
(dataEARLY and dataLATE). Use Delay 2 to shift output clock accordingly such that both flags are OFF. Then, correct timing (input data to internal IP clock) are centered and robust input data sampling is achieved.

This DAC  is designed to excel in a wide range of applications, making it ideal for high-speed transceiver systems where precision and reliability are crucial. Its versatile design and configurable features cater to both wireline and wireless transmitters, ensuring seamless integration into advanced communication networks.

The DAC’s high-speed performance and precise clock phase adjustments make it a valuable component in optical networking systems, where efficient and accurate signal processing is essential. Additionally, the chip’s adaptability makes it suitable for automotive applications, meeting stringent industry standards for in-vehicle communication and control systems. The DAC10_1GS_28HPC+_DUAL is also well-suited for software-defined radio (SDR) platforms, enabling flexible and dynamic signal processing in modern telecommunication and broadcasting systems.

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